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Cadence SPB OrCAD 16.50.036/16.60.002 Hotfix (x32)

Cadence SPB OrCAD 16.50.036/16.60.002 Hotfix (x32) | 924.3 mb

This release includes the latest fixes for Cadence SPB OrCAD 16.5 and Cadence SPB OrCAD 16.6 platform.

New technologies in Allegro and OrCAD 16.5 include advanced miniaturization capabilities, integrated power delivery network analysis, DDR3 design-in kit, bolstered co-design featured and flexible team-design enablement to address global designer productivity.

"Cadence SPB OrCAD 16.50.036/16.60.002 Hotfix (x32)"

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Cadence SPB OrCAD 16.50.036/16.60.002 Hotfix (x32)

Cadence SPB OrCAD 16.50.036/16.60.002 Hotfix (x32) | 924.3 mb

This release includes the latest fixes for Cadence SPB OrCAD 16.5 and Cadence SPB OrCAD 16.6 platform.

New technologies in Allegro and OrCAD 16.5 include advanced miniaturization capabilities, integrated power delivery network analysis, DDR3 design-in kit, bolstered co-design featured and flexible team-design enablement to address global designer productivity.


DATE: 01-18-2013 HOTFIX VERSION: 036
CCRID PRODUCT PRODUCTLEVEL2 TITLE

491042 CONCEPT_HDL SECTION Prevent PackagerXL from changing visibility on SEC attribute
945393 FSP OTHER group contigous pin support enhancement
1005078 CAPTURE ANNOTATE Copy paste operation does not fill the missing refdes
1018756 CONCEPT_HDL CONSTRAINT_MGR Match Groups with Pin Pairs are not getting imported into the schematic CM during Import Physical
1032609 FSP IMPORT_CONSTRAIN Import qsf into FSP fails with PLL PLL_3 does not exist in device instance
1071037 PSPICE SIMULATOR Provide option to disable Index Files Time Stamp Check
1073237 SIG_INTEGRITY GEOMETRY_EXTRACT Some nets has no result at Bus Simulation and Comprehensive simulation.
1076898 CONCEPT_HDL CORE User can not increase logic grid size value continuously using Up button on Design Entry HDL Options
1077169 APD SHAPE Shape > Check is producing bogus results.
1078270 SCM UI Physical net is not unique or not valid
1078497 ALLEGRO_EDITOR INTERFACES Import DXF does not seem to work correctly.
1079821 CONCEPT_HDL CORE Project Setup does not respect $TEMP variable for temp_dir and creates a directory in project calle
1080336 CONCEPT_HDL CORE Backannotation error message ehnancement
1080982 CONCEPT_HDL CORE Crash of Allegro Design Entry during a copy of a note.
1081200 CONSTRAINT_MGR OTHER In the DIFF_PAIR worksheets various Analysis seem to take a long time to complete.
1081553 CONCEPT_HDL OTHER Model Assignment can not translate M (Milli-ohm) property value of DE HDL.
1081696 ALLEGRO_EDITOR INTERACTIV Compose shape not working when radius is set to 1.0
1081760 FSP CONFIG_SETTINGS Content of FPGA Input/Output Onchip termination columns resets after update csv command
1081834 CONCEPT_HDL OTHER PDF Publisher fails crashes DEHDL
1082220 FLOWS OTHER Error SPCOCV-353
1082785 CONCEPT_HDL CORE DE HDL should clean the design with non sync properties in some automated way
1083533 CONCEPT_HDL CONSTRAINT_MGR Bug -Net-count under few of the netclasses are not in sync between Schematics & Layout
1083637 PCB_LIBRARIAN CORE Save As is not renaming the NAME in the symbol.css file
1084148 CONCEPT_HDL CHECKPLUS The CheckPlus hasProperty predicate fails in the Physical environment.
1084285 CONCEPT_HDL INFRA Corrupted dcf was never fixed and caused PXL error
1084441 CONCEPT_HDL CORE Assigned net property value changes to numeric
1084542 ALLEGRO_EDITOR DRAFTING Dimensions associated with frect doesn't rotate with the symbol.
1084736 APD IMPORT_DATA Import SPD2 file from UPD-L shape Pad and text issue
1085008 ALLEGRO_EDITOR INTERACTIV Relative (from last pick) option in the Pick dialog not working for pick command
1085010 CONCEPT_HDL CREFER Crefer crashes if the property value in the dcf file has more than 255 characters
1086576 CONCEPT_HDL CHECKPLUS CheckPlus hangs when running Graphic rules.
1086902 CONCEPT_HDL INFRA Problems occurred while loading design connectivity
1086905 PSPICE SIMULATOR PSpice crash while simulating circuit file with BREAK function
1087658 CAPTURE PRINT/PLOT/OUTPU Lower level design pages are getting print twice
1087770 ALLEGRO_EDITOR EDIT_ETCH Allegro crashes on a pick with the slide command.
1088231 F2B PACKAGERXL Design fails to package in 16.5
1090838 SIP_LAYOUT PLATING_BAR Can't create palting Bar

Cadence Design Systems, Inc., a leader in global electronic design innovation, launched the Cadence OrCAD 16.6 design solution with new features, enhanced customization capabilities, and 20 percent simulation performance improvements that provide customers a shorter, more predictable path to product creation.

This latest release offers numerous improvements to tool usability and performance, but at the heart of 16.6 are three key benefits: enhanced miniaturization capabilities, timing-aware physical implementation and verification for faster timing closure, and the industrys first electrical CAD team collaboration environment for PCB design using Microsoft SharePoint technology.

DATE: 12-21-2012 HOTFIX VERSION: 002
CCRID PRODUCT PRODUCTLEVEL2 TITLE

491042 CONCEPT_HDL SECTION Prevent PackagerXL from changing visibility on SEC attribute
863928 ALLEGRO_EDITOR INTERACTIV Segment over void higlights false "nets with arc"
1067272 PCB_LIBRARIAN CORE Unable to retain the symbol outline changes
1074820 ALLEGRO_EDITOR GRAPHICS losing infinite cursor tracking after selecting the add text command with opengl enable
1075622 CONCEPT_HDL CORE PDV Edit Symbol in DE-HDL all editing functions disabled since Hotfix 33
1076986 APD WIREBOND Wirebond Adjust Min DRC does not maintain the finger position in the same sequence
1078031 SIG_INTEGRITY REPORTS Requesting improvement to progress indicator for report generator
1080213 SIP_LAYOUT WIREBOND Wrong behavior of Redistribute Fingers Command
1080667 ALLEGRO_EDITOR GRAPHICS Allegro lines with fonts not displayed correctly in 16.6
1080982 CONCEPT_HDL CORE Crash of Allegro Design Entry during a copy of a note.
1081200 CONSTRAINT_MGR OTHER In the DIFF_PAIR worksheets various Analysis seem to take a long time to complete.
1081553 CONCEPT_HDL OTHER Model Assignment can not translate M (Milli-ohm) property value of DE HDL.
1081696 ALLEGRO_EDITOR INTERACTIV Compose shape not working when radius is set to 1.0
1082595 ALLEGRO_EDITOR COLOR Infinite cursor remains white even we change background to white
1082704 ALLEGRO_EDITOR GRAPHICS infinite cursor disappears when using Display>Measure
1082715 SIG_EXPLORER INTERACTIV Single line impedance for BOTTOM Layer is not calculated in cross section upon changing the thickness of dielectic layer
1082774 ALLEGRO_EDITOR TECHFILE Import techfile command terminates abnormally when importing a generic techfile.
1082820 CONSTRAINT_MGR UI_FORMS The configure generic cross-section pull downs do not work.
1083133 SIP_LAYOUT INTERACTIVE SiP will crash when using the beta Pad Rename command to change a BGA pads name.
1083158 ALLEGRO_EDITOR GRAPHICS The cursor chage to Arrow head for Shape Select is more sensitive to location in SPB 16.6
1083533 CONCEPT_HDL CONSTRAINT_MGR Bug -Net-count under few of the netclasses are not in sync between Schematics & Layout
1083637 PCB_LIBRARIAN CORE Save As is not renaming the NAME in the symbol.css file
1083934 ALLEGRO_EDITOR PAD_EDITOR Error(SPMHUT-41): File selected is not of type Drawing.
1084148 CONCEPT_HDL CHECKPLUS The CheckPlus hasProperty predicate fails in the Physical environment.
1084166 SIP_LAYOUT DIE_ABSTRACT_IF Updating sip layout with new die abstract doesn't properly update IC_DESIGN_CELL* properties
1084285 CONCEPT_HDL INFRA Corrupted dcf was never fixed and caused PXL error
1084441 CONCEPT_HDL CORE Assigned net property value changes to numeric
1084542 ALLEGRO_EDITOR DRAFTING Dimensions associated with frect doesn't rotate with the symbol.
1084736 APD IMPORT_DATA Import SPD2 file from UPD-L shape Pad and text issue
1085008 ALLEGRO_EDITOR INTERACTIV Relative (from last pick) option in the Pick dialog not working for pick command
1085139 ALLEGRO_EDITOR GRAPHICS Infinite Cursor disappear during Add Connect if Infinite_cursor_bug_nt is enabled
1085187 SIP_LAYOUT INTERFACE_PLANNE netrev with overwrite constraints fatal error
1086402 ALLEGRO_EDITOR GRAPHICS Infinite cursor dissapear when using command like add connect or Place manually with opengl enabled.
1086905 PSPICE SIMULATOR PSpice crash while simulating circuit file with BREAK function
1087770 ALLEGRO_EDITOR EDIT_ETCH Allegro crashes on a pick with the slide command.
1088412 SCM CONCEPT_IMPORT why reimport block adds _1 to the netnames?
1088958 CONSTRAINT_MGR INTERACTIV annot create Differential Pairs out of nets that belongs to a Net Group
1089336 ALLEGRO_EDITOR GRAPHICS infinite cursor and pcb_cursor_angle
1090689 ADW LRM LRM: Unable to select any Row regardless of Status
1090955 ALLEGRO_EDITOR OTHER Cancel command crashes PCB Editor when add rectangle
1091047 ALLEGRO_EDITOR REPORTS The "Dangling Lines Via and Antenna report seems to be missing vias that are antennas.
1091218 ADW LRM LRM is not worked for the block design of included project
1091443 ALLEGRO_EDITOR OTHER Crash when toggling suppress pads
1091706 ALLEGRO_EDITOR EDIT_ETCH Allegro crash while routing after setting variable acon_no_impedance_width
1092916 CAPTURE OTHER Capture crash
1093573 ALLEGRO_EDITOR DATABASE team design opening workflow manager crashes allegro. possibly corrupt database

About Cadence Design Systems, Inc.
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry.

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